EMIF10-LCD03F3
10-line IPADTM, EMI filter and ESD protection
Features
High attenuation in the mobile frequency range (typically better than -40 dB from 900 MHz to 2 G H z) Very low clamping voltage Low line capacitance (30 pF max) suitable for high-speed interfaces Maximum rise and fall time: 6 ns (10% - 90%) Compliant with high speed data rate Lead-free Flip Chip package in 400 m pitch Very thin package: 0.6mm thickness
Flip Chip (24 bumps)
Description
The EMIF10-LCD03F3 is a 10-line highly integrated LC filter designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF10 Flip Chip packaging means the package size is equal to the die size. This LC filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV. Figure 1. Pin layout (bump side)
5
O1 O3 O5 O7 O9
Benefits
High efficiency in EMI filtering High bandwidth: typically 200 MHz at -3 dB 80% space saving versus discrete solution (BOM reduction) High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging
4
O2 O4 O6 O8 O10
3
GND
2
I1 I3
1
I2 I4 I6 I8 I10
A B C D E
Complies with the following standards
IEC61000-4-2 level 4 on inputs and outputs 15 kV (air discharge) 8 kV (contact discharge)
GND
I5 I7 I9
GND
GND
Applications
Displays and cameras where outstanding EMI filtering in ESD sensitive equipment is required:
Figure 2.
Device configuration
Low-pass Filter
0000
Mobile phones and PDAs Personal and home entertainment (portable audio, DVD players, LCD TVs) Portable navigation devices Digital still cameras Portable gaming systems
Input
Output
GND
GND
Ri/o = 125 20% Cline = 30 pF max
GND
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 1
1/7
www.st.com 7
Characteristics
EMIF10-LCD03F3
1
Characteristics
Table 1.
Symbol
Absolute maximum ratings (Tamb = 25 C)
Parameter Input and output pins: ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge Maximum junction temperature Operating temperature range Storage temperature range Value Unit
VPP Tj Top Tstg
15 15 125 -40 to +85 -55 to 150
kV
C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IP P RI/O Cline Symbol VBR IRM RI/O Cline
Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage
IF I
Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input & Output Line capacitance Test conditions IR = 1 mA VRM = 3 V per line Tolerance 20% Vline = 0 V, VOSC = 30 mV, F =1 MHz 100 125 Min 14 200 150 30 Typ Max Unit V nA pF
IPP VCL VBR VRM IRM IR VF V
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EMIF10-LCD03F3
Characteristics
Figure 3.
0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00
S21 measurement (all GND bumps connected)
Figure 4.
dB
Analog crosstalk measurements (all GND bumps connected)
dB
0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00
F (Hz)
100.0k
I1- O1 I3- O3 I5- O5 I7- O7 I9-O9
-110.00 -120.00
1.0M
10.0M
100.0M
I2- O2 I4- O4 I6- O6 I8- O8 I10-O10
1.0G
-130.00 -140.00 100.0k I1-O2 1.0M 10.0M
F (Hz)
100.0M I1-O10 1.0G
Figure 5.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on one line
Figure 6.
ESD response to IEC 61000-4-2 (-15 kV air discharge) on one line
Figure 7.
Line capacitance versus applied voltage (typical values)
30
Cline (pF)
F=1 MHz VOSC = 30 mVRMS TJ = 25 C
25
20
15
10
5 Vline (V) 0 0 1 2 3 4 5
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Ordering information scheme
EMIF10-LCD03F3
Figure 8.
Typical rise and fall time: input voltage
Figure 9.
Typical rise and fall time: output voltage
INPUT VOLTAGE
X: 10 ns/DIV Y: 1 V/DIV
OUTPUT VOLTAGE X: 10ns/DIV Y: 1V/DIV Trise10% -90% = 3.45 ns Tfall 90%-10% = 4.09 ns
2
Ordering information scheme
Figure 10. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10 (pF) or 3 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 m
yy
-
xxx zz
F3
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EMIF10-LCD03F3
Package information
3
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Package dimensions
400 m 40
400 m 40
255 m 40
605 m 55
190 m 10
240 m 10
1.98 mm 30 m
Figure 12. Footprint
Copper pad Diameter: 220 m recommended 260 m maximum Solder mask opening: 300 m minimum
Figure 13. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
2.08 mm 30 m
E
Solder stencil opening: 220 m recommended
xxz y ww
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Ordering information Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1
EMIF10-LCD03F3
Ø 1.5 0.1
1.75 0.1 3.5 0.1
2.13
0.69 0.05
All dimensions in mm
8 0.3
ST E
ST E
ST E
xxz yww
User direction of unreeling
xxz yww
xxz yww
4 0.1
2 .2 2
Note:
More information is available in the application notes: AN2348: "STMicroelectronics 400 micro-metre Flip Chip: Package description and recommendation for use" AN1751: "EMI Filters: Recommendations and measurements"
4
Ordering information
Table 3. Ordering information
Marking HI Package Flip Chip Weight 5.3 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF10-LCD03F3
5
Revision history
Table 4.
Date 14-Apr-2008
Document revision history
Revision 1 Initial release Changes
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EMIF10-LCD03F3
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